This invention pertains to active matrix liquid crystal displays and particularly to display pixels. More particularly, the invention pertains to pixel electrodes of displays.
Active matrix liquid crystal displays (AMLCDs) are being used as a replacement for cathode ray tubes (CRTs) in a number of select applications, as well as in new applications such as laptop and note-book personal computers (PCs) wherein CRTs were not even considered due to their bulky size, excessive weight, and high power consumption. However, the use of AMLCDs is limited by the high cost of these displays due to complex fabrication processes used and the low yields achieved. Amorphous silicon (a-Si) thin film transistors (TFTs) are most widely used in the active matrix array for the fabrication of AMLCDs, because of their low temperature processing feature and large area capability.
Indium tin oxide (ITO) is used as a transparent pixel electrode in the fabrication of AMLCDs. While ITO material has good transmission and electrical conductivity, it complicates the active matrix substrate processing. Some of the thin films used in the fabrication of a-Si TFTs are not completely compatible with the ITO pixel electrode layer with respect to processing temperatures and adhesion properties. This incompatibility requires trade-offs in design and fabrication that affect process complexity, display performance and cost.
FIGS. 1a and 1b illustrate the conventional design of a typical a-Si TFT and pixel having ITO as a pixel electrode material. FIG. 1a shows the cross-sectional view and FIG. 1b shows the plan view. Even though there may be variations in details among the different processes used, a typical a-Si TFT active matrix substrate fabrication involves the following steps: 1) deposit, pattern and etch the gate metal layer 11 such as chromium on the display glass substrate 10; 2) deposit the gate dielectric layer such as silicon nitride 12; 3) deposit, pattern and etch undoped a-Si layer 13; 4) deposit dielectric masking layer 14 such as silicon dioxide; 5) pattern and etch layer 14 which defines the TFT channel length and serves as a mask for source and drain contact formation; 6) form source and drain contacts 15 by deposition of a thin (about 200 Angstroms), highly phosphorus doped a-Si (n.sup.+ a-Si) layer 15; 7) deposit a source-drain metal such as aluminum layer 16, and pattern and etch aluminum layer 16 and n.sup.+ a-Si layer 15; 8) deposit a passivation layer 17 such as silicon dioxide; 9) pattern and etch pixel contact vias 9 in layer 17; 10) deposit, pattern and etch ITO pixel electrode 18; and 11) deposit, pattern and etch a dark polyimide layer 19. This dark polyimide layer is electrically non-conducting and serves as a top light shield layer for the TFT. Gate metal layer 11 serves as a bottom light shield layer for the TFT.
The above related art process is complicated, and involves design and performance trade-offs due to the use of an ITO pixel electrode 18. For example, if ITO layer 18 simply were to be deposited on the aluminum source-drain metal 16 directly, without an intermediate passivation layer 17 having contact via 9, significant film stresses would occur and result in the peeling of the aluminum/ITO layers 16 and 18. Thus, the use of passivation layer 17 with contact via 9, though a process complication, minimizes the contact area of aluminum/ITO layers 16 and 18, and keeps the film stresses manageable.